A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.
References
Configurations
No configuration.
History
No history.
Information
Published : 2025-11-10 20:15
Updated : 2025-11-12 21:15
NVD link : CVE-2025-63384
Mitre link : CVE-2025-63384
CVE.ORG link : CVE-2025-63384
JSON object : View
Products Affected
No product.
CWE
CWE-266
Incorrect Privilege Assignment
